| October 23, 2012 |
Session 1: Opening Session
Chairperson : J. Koike |
| 9:30-9:50 |
Opening Remarks: H. Kawasaki, Chair of Asian Session [Mitsubishi
Heavy Industries]
Award Ceremony |
9:50-10:30
(1-1) |
Keynotes: Reliability Challenges for 3D Interconnects
Containing Through Silicon Vias: A Material
and Processing Perspective [Univ. of Texas
at Austin] Paul S. Ho et al. |
10:30-11:10
(1-2） |
Keynotes: Spintronics-based Nonvolatile CMOS VLSI [CSIS/WPI-AIMR/RIEC,
Tohoku Univ.] H. Ohno |
Session 2: Crucial Metal Technologies
Chairperson : F. Ito |
11:10-11:40
(2-1） |
Invited: Integration Concerns for Metallization [1IBM, 2Global Foundries, 3Renesas Electronics] T. Spooner1, J. H. Chen1, T. Nogami1, M. He2, and M. Tagami3 |
11:40-12:00
(2-2） |
Simultaneous Formation of a Metallic Mn Layer
and a MnOx / MnSixOy Barrier
Layer by Chemical
Vapor Deposition at 250oC [1Tohoku Univ., 2LEAP, 3TEL Tech. Center, 4Ube Industries] A. Kurokawa1, Y. Sutou1, J. Koike1, T. Hamada2, K. Matsumoto2, H. Nagai2, K. Maekawa3, and H. Kanato4 |
12:00-12:20
(2-3） |
Improvement of Stress Induced Voiding by
Controlling Microstructure of Cu Electroplated
Films [Renesas Electronics] S. Muranaka,
K. Omori, K. Mori, R. Shibata, N. Suzumura,
S. Kudo, and M. Fujisawa |
| 12:20-13:30 |
(Lunch Break 1 hour 10 min) |
Session 3: Chemical Mechanical Polishing
Chairpersons : K. Okutani / S. Kondo |
13:30-13:50
(3-1-1） |
The Impact of Diamond Conditioners on Scratch
Formation during Silicon-dioxide CMP [Hanyang
Univ.] T.-Y. Kwon, M. Ramachandran, B.-J.
Cho, A. A. Busnaina, and J.-G. Park |
13:50-14:10
(3-2） |
Study of Polishing Mechanism of SiO2 by CeO2 Abrasive Grain [Noritake] W. Omori, and
M. Sato |
14:10-14:30
(3-3） |
Study on Contact Image Analysis Between Polishing
Pad and Wafer During CMP
[Kyushu Inst. of
Tech.] K. Suzuki, E. Okamoto,
P. Khajornrungruang,
and K. Kimura |
14:30-14:50
(3-4） |
SiC-CMP Processing Characteristics under
Different Atmospheres Using MnO2 Slurry with Strong Oxidant [1Kyushu Univ., 2Univ. of Miyazaki] Z. Tan1, T. Doi1, S. Kurokawa1, O. Ohnishi2, T. Yamazaki1, T. Yin1 |
14:50-15:10
(3-6） |
Cu-CMP Corrosion in Barrier-less Cu Damascene
Structure Caused by Concentration-Cell
Effect
[CASMAT] K. Okutani |
| 15:10-15:30 |
(Break 20 min) |
Session 4: 3D challenges
Chairperson : T. Nakamura |
15:30-16:00
(4-1） |
Invited: Development of 3D Integration Technologies
and Recent Challenges [Tohoku Univ.] T Fukushima,
K.-W. Lee, T. Tanaka, and M. Koyanagi |
16:00-16:20
(4-2） |
Impacts of Thermo-Mechanical Stresses on
Bumpless Chip in Stacked Wafer Structure
[1Fujitsu Lab., 2Univ. of Tokyo] Y. Mizushima1,2, H. Kitada1,2, C. J. Uchibori1, N. Maeda2, S. Kodama2, Y. Kim2, K. Fujimoto2, S. Yoshimi2, T. Nakamura1, and T. Ohba2 |
16:20-16:40
(4-3） |
Development of Dielectric Polymer Etching
for Chip-on-Wafer Process using Bump-less
Off-Chip-Via Interconnects. [1Dai Nippon Printing, 2Univ. of Tokyo, 3DISCO, 4Fujitsu Lab.] S. Yoshimi1, M. Akazawa1, K. Fujimoto1, K. Suzuki1, N. Maeda2, Y. S. Kim2, H. Kitada2, S. Kodama3, Y. Mizushima4, and T. Ohba2 |
16:40-17:00
(4-4） |
The TSV (Through Silicon Via) Filled with
the Nanotwined Cu [Hanyang Univ.] S. Jin,
S. Seo, and B. Yoo |
|
| October 24, 2012 |
Session 5: Advanced Metal Processes
Chairperson : H. Shibata / N. Shimizu |
9:00-9:30
(5-1） |
Invited: Metal ALD and CVD [1Hanyang Univ., 2SK Hynix Semiconductor ] J. Park1, T. Park2, J. Lee1, H. Jeon1, and H. Jeon1 |
9:30-9:50
(5-2） |
Adhesion and Nucleation Property of CVD-Cu
with ALD-Co(W) Film as
Cu Diffusion Barrier
and Adhesion Promoting
Layer in Future ULSI
Interconnects [Univ. of
Tokyo] K. Shima,
H. Shimizu, T. Momose,
and Y. Shimogaki |
9:50-10:10
(5-3） |
Process Design for Co(W) Alloy Films as a
Single Layered Barrier/Liner
Layer for 14
nm Generation Cu-interconnect
[1Univ. of Tokyo2, Taiyo-Nippon Sanso] H. Shimizu1, 2, A. Kumamoto1, Y. Suzuki1, K. Shima1, T. Momose1, and Y. Shimogaki1 |
| 10:10-10:30 |
(Break 20 min) |
10:30-11:00
(5-4） |
Invited: Comprehensive Cu Diffusion Barrier Testing
of Co-W Thin Flms Prepared by PVD, CVD and
ALD [Technische Univ. Dresden] H. Wojcik,
H. Shimizu, Y. W. Bartha, and Y. Shimogaki |
11:00-11:20
(5-5） |
Grain Size and Texture Investigation of Cu
Wire Formed with Additive-free Plating by
EBSD [Ibaraki Univ.] Y. Ke, T. Namekawa,
K. Tamahashi, and J. Onuki |
11:20-11:40
(5-6） |
Performance of Integrated Cu Gap-fill Process
with CVD-Co Liner [ULVAC] Y. Kokaze, S. Kodaira,
Y. Endo, J. Hamaguchi, M. Harada, S. Kumamoto,
Y. Sakamoto, and Y. Higuchi |
11:40-12:00
(5-7） |
Pt Deposition as an Electrode for FeRAM Using
SCFD [Univ. of Tokyo] S.
Suita, T. Momose,
and Y. Shimogaki |
| 12:00-13:30 |
(Lunch Break 1 hour 30 min) |
Session 6: Reliability and Contacts
Chairperson : S. Yokogawa / O. Nakatsuka |
13:30-14:00
(6-1） |
Invited: Study of Electromigration Voiding Mechanisms
in Cu Interconnects with Doping Elements
for 28 nm Technology Node and Beyond [1CEA/LETI, 2ST Microelectronics] L. Arnaud1,2 A. Ponvert2, S. Blonkowski2 |
14:00-14:20
(6-2） |
Local Deformation and Interfacial Fracture
Behavior of Cu/Dielectric
Systems in Interconnect
Structures [1Nagoya Inst. of Tech., 2JST, 3Keio Univ., 4Fujitsu Lab.., 5JEOL] H. Sato1, 2, N. Shishido1, 2, S. Kamiya1, 2, K. Koiwa1, 2, M. Omiya2, 3, M. Nishida1, 2, T. Suzuki2, 4, T. Nakamura2, 4, T. Nokuo2, 5, and T. Nagasawa2, 5 |
14:20-14:40
(6-3） |
Reliability Tests of Eleｃｔｒoless Barriers
against Copper Diffusion
under Bias Temperature
Stress with n-and Type
Substrates [Shibaura
Inst. of Tech.] M. Yamashita,
S. Fujishima,
A. Mitsumori, and K. Ueno |
14:40-15:00
(6-4） |
Formation and Stress Characterization of
NiGe/Ge(110) and Ge(001）
Contacts [Nagoya
Univ.] Y. Deng, J. Yokoi,
O. Nakatsuka, and
S. Zaima |
15:00-15:20
(6-5） |
The Influence of Ni Film Thickness on NiSi2
Formation on a Si (001） Substrate at Low
Temperatures by High-resolution Scanning
Transmission Electron Microscopy [Renesas
Electronics] Y. Sakura, and N. Ikarashi formation
on a Si (001） substrate at low temperatures
by high-resolution scanning transmission
electron microscopy [Renesas Electronics]
Y. Sakurai, and N. Ikarashi |
| 15:20-15:40 |
Guest speaker from AMC [Univ. of Tokyo] T. Ohba |
| 15:40-15:50 |
(Break 10 min) |
Poster Session (15:50-17:20)
Chairperson : E. Kondoh |
| P-1 |
Study of the Wafer Bow Variation During Re-distribution
Layer (RDL) and Probe Pad Formation for 3DIC
Wafer-on-Wafer (WOW) Application [1ITRI, 2Univ. of Tokyo] S. C. Liao1, C. H. Lin1, E. H. Chen1, T. Ohba2, Y. S. Kim1, S. Kodama2, K. Fujimoto2, H. Kitada2, N. Maeda2, P. J. Tzeng1, J. C. Chen1 , S. C. Chen1, C. Y. Wu1, C. C. Chen1, Y. C. Hsin1, C. H. Chen1, C.C. Wang1, T. C. Hsu1, T. K. Ku1, and M. J. Kao1 |
| P-2 |
Improvement of Adhesion Strength of Electroless
Barrier Layer on SiO2 and Control of Deposition Profile in a High
Aspect ratio TSV [Kansai Univ.] S. Nishizawa,
F. Inoue, R. Arima, T. Shimizu, and S. Shingubara |
| P-3 |
ZnO Adhesion Layer for Nanoprecision Electroless-Cu/glass
Metallization [Univ. of Yamanashi] A. Teraoka,
M. Watanabe, Y. Nabetani, and E. Kondoh |
| P-4 |
Conformal Resist Coating Technique in the
Trough-Silicon Via (TSV)
with a Rotary Atomizer
Aerosol Spray [1Asahi Sunac, 2Kyushu Univ.3, Tokyo Ohka Kogo] Y. Seike1, M. Ohtsubo2, K. Maruyama3, F. Shimai3, H. Akenaga, H. Morishita, K. Miyachi, M.
Amari1, T. Doi2 and S. Kurokawa2 |
| P-5 |
Study on the Design of Through-Silicon Via
(TSV) Liner upon Its Mechanical
Properties
[United Microelectronics]
C.-W. Lo, J.-M.
Chen, Y.-H. Tsai, and C.-C.
Liu |
| P-6 |
Electrical Contact Property and Interface
Microstructure of Cu-Si Alloy on n-GaAs [Tohoku
Univ.] B. T. Bae, and J. Koike |
| P-7 |
Determination of Current Density Suppression
Ability of Poly (Ehylene Glycol) During Copper
Electrodeposition by an EQCM and a Microfluidic
Device [Osaka Pref. Univ.] T. Saito, Y. Tsujimoto,
Y. Miyamoto, N. Okamoto, and K. Kondo |
| P-8 |
Analysis of Electrodeposited Nano-scale Copper
Wire Microstructure by EBSD Method [1Ibaraki Univ., 2Tohoku Univ.] T. Konkova1, Y. Ke1, S. Mironov2, J.Onuki1 |
| P-9 |
Etched Profile Control in H2/N2 Plasma with Radical Density Monitoring [1Nagoya Univ., 2Osaka Univ., 3Kyushu Univ., 4JST-CREST] T. Suzuki1, A. Malinowski1, K. Takeda1,4, H. Kondo1, K. Ishikawa1, Y. Setsuhara2,4, M. Shiratani3,4, M. Sekine1,4, M. Hori1,4 |
| P-10 |
Fabrication and Evaluation of Nanowire-based
Resistive Switching Device Using Self-organized
Template [Kansai Univ.] T. Kyomi, S. Otsuka,
Y. Takeda, Y. Sumita, T. Shimizu, and S.
Shingubara |
| P-11 |
Numerical Simulations of High Heat Dissipation
Technology in LSI 3-D Packaging
Using CNT
Through Silicon Via (TSV)
and Thermal Interface
Material (TIM) [1Keio Univ., 2GNC/AIST] T. Kawanabe1, M. Nihei2, and Y. Awano1 |
| P-12 |
Evaluation of Surface Damaged Layer Depth
of Si wafer for TSV [1Kyushu Univ., 2Kanazawa Inst. of Tech., 3Univ. of Miyazaki, 4Mitsubishi Chemical] S. Iwamoto11, S. Kurokawa1, T. Doi1, M. Uneda2, O. Ohnishi3, T. Suzuki4, Y. Kawase4, and K. Harada4 |
| P-13 |
Characteristics of Sapphire CMP Under Various
Gas Conditions Using Belll-Jar
Type CMP Machine
[1Kyushu Univ., 2Univ. Miyazaki, 3Kanazawa Inst. of Tech., 4Koshiyama Science and Tech. Foundation, 5Fujikoshi Machinery] T. Egashira1, T. Doi1, S. Kurokawa1, O. Ohnishi2, M. Uneda3, I. Koshiyama4, and D. Ichikawa5 |
| P-14 |
SiC-CMP Processing Characteristics under
Different Atmospheres Using MnO2 Slurry with Strong Oxidant [1Kyushu Univ., 2Univ. of Miyazaki] Z. Tan1, T. Doi1, S. Kurokawa1, O. Ohnishi2, T. Yamazaki1, T. Yin1 |
| P-15 |
Evaluation for In-Plane Micro-Deformation
Distribution Characteristics
of Polishing
Pad Surface Texture [1Kanazawa Inst. of Tech., 2Fujikoshi Machinery] M. Uneda1, T. Omote1, K. Shibuya2, Y. Nakamura2, D. Ichikawa2, and K. Ishikawa1 |
| P-16 |
Modification of Diamond Conditioner with
V-SAM Coatings for Corrosion
Prevention during
Metal CMP [Hanyang Univ.]
B.-J. Cho, R. P.
Venkatesh, T.-Y. Kwon,
and J.-G. Park |
| P-18 |
A Novel on-site Cupric Oxide Recovery Process
from Waste Containing Copper
[Swing] T. Kobayashi,
K. Kano, T. Suzuki, and
A. Kobayashi |
| P-19 |
Hybrid Cleaning Technology for Enhanced Post-Cu/low-k
CMP Cleaning Performance
[Hanyang Univ.]
M. Ramachandran, B.-J.
Cho, T.-Y. Kwon, and
J.-G. Park |
| P-20 |
Advanced PCMP Formulation with Cobalt Compatibility
[ATMI] J. Liu, L. Sun,
J. Chang, and C. Tran |
| P-21 |
Development of the Fabrication Process of
Ni mold for Nano-imprint Using Supercritical
Carbon Dioxide [Univ. of Tokyo] H. Kawada,
T. Momose, and Y. Shimogaki |
| P-22 |
Development of Technique for Embedding Cu
into 15-nm-wide Trench
by High-Vacuum Magnetron
Sputtering Method [Tokyo
Univ. of Science]
M. Itoh, H. Iida , and
S. Saito |
| P-23 |
New Cu-SnNx AlloyFilms for Better Copper
Interconnects [Asia-Pacific
Inst. of Creativity]
C.H.Lin |
| P-24 |
Dependence of Crystal Structure of Electrodeposited
Co/Cu Multilayers on Nanometric
Layer Thickness
[1Nagano Pref. General Industrial Tech. Center,
2Shinshu Univ.] .N Takane1,2, H. Narita1, and S. Arai2 |
| P-25 |
Preparation Conditions of Nano-crystalline
ZrNx Films by Reactive Sputtering [1Kitami Inst. of Tech., 2Tohoku Univ.] M. B. Takeyama1, M. Sato1, E. Aoyagi2, and A. Noya1 |
| P-26 |
Hot-wire-assisted Atomic Layer Deposition
of High Quality Nickel
Films [Univ. of Tokyo]
G. Yuan, H. Shimizu, T.
Momose, and Y. Shimogaki |
| 17:20-17:40 |
(Break 20 min) |
Sponsored Banquet (17:40-19:10)
|
|
| October 25, 2012 |
Session 7: Nanocarbon
Chairperson Y. Awano / K. Ueno |
9:00-9:30
(7-1） |
Invited: Graphene Nanoribbon Interconnects [Georgia
Inst. of Tech.] V. Kumar, S. Rakheja, and
A. Naeemi |
9:30-10:00
(7-2） |
Invited: Synthesis of Nanocarbon Materials and Their
Interconnect Application [AIST] S. Sato,
M. Nihei, and N. Yokoyama |
| 10:00-10:10 |
(Break 10 min) |
10:10-10:30
(7-3） |
Resistance of Multi-layer Graphene Wire for
Interconnects [LEAP] H.
Miyazaki, M. Katagiri,
Y. Yamazaki, M. Suzuki,
M. Wada, M. Kitamura,
T. Saito, A. Isobayashi,
A. Sakata, N. Sakuma,
A. Kajita, and T. Sakai |
10:30-10:50
(7-4） |
Low-resistance Metal Contacts to Nanocarbon/Cobalt
Interconnects [1Shibaura Inst. of Tech., 2LEAP] M. Takagi1, H. Yano1, T. Wakui1, N. Sakuma2, A. Kajita2, T. Sakai2, and K. Ueno1 |
10:50-11:10
(7-5） |
Resistance Factors in Carbon Nanotube Via
Interconnects [LEAP] M.
Katagiri, M. Suzuki,
Y. Yamazaki, H. Miyazaki,
B. Ito, D. Nishide,
T. Matsumoto, M. Wada,
M. Kitamura, T. Saito,
A. Isobayashi, A. Sakata,
M. Watanabe, N.
Sakuma, A. Kajita, and
T. Sakai |
11:10-11:30
(7-6） |
A New Microstrip Open-Stub Structure with
Carbon Nanotube Bumps for
Shrinking Distributed
Passive Components in MMICs
[1Keio Univ., 2Fujitsu Lab.] M. Nakamura1, T. Iwai2 and Y. Awano1 |
| 11:30-12:40 |
(Lunch Break 1 hour 10 min) |
Session 8: Low-k
Chairperson : T. Nemoto |
12:40-13:10
(8-1） |
Invited: Molecularly Tailored Nanomaterials and Metal-dielectric
Interfaces for Electronics and Energy Harvesting
[Rensselaer Polytechnic Inst.] G. Ramanath |
13:10-13:40
(8-2） |
Invited: Low-k Material Design and Process Optimization
for Plasma Damage Reduction in High-reliable
22nm-Node Cu Dual Damascene Interconnects
[1Renesas Electronics, 2IBM] F. Ito1, H. Shobha2, M. Tagami1, T. Nogami2, S. Cohen2 Y. Ostrovski2, S. Molis2, K. Maloney2, J. Femiak2, J. Protzman2, T. Pinto2, E. T. Ryan2, A. Madan2, C.-K. Hu2, and T. Spooner2 |
13:40-14:00
(8-3） |
Airgap Formation in Ultra Fine Wire Spacing
and Its Wire-to-Wire Leakage Characteristics
[Toshiba] H. Miki, A. Isobayashi, A. Kajita,
Y. Sugizaki, and H. Shibata |
14:00-14:20
(8-4） |
PEALD Sealing Property on Extreme Low-k Film
with k=2.0 Quantified by Mass Metrology [1ASM, 2Metryx] A. Kobayashi1, A. Nakano1, Y. Kimura1, D. Ishikawa1, K. Matsushita1, N. Kobayashi1, G. Ditmer2, A. Kiermasz2 |
| 14:20-14:35 |
(Break 15 min) |
Session 9: Backend devices Technology
Chairpersons : M. B. Takeyama / M. Tada |
14:35-15:05
(9-1） |
Invited: Materials and Process Aspect of ReRAM and
Selector Device for Cross-point
Memory Applications
[POSTECH] H. Hwang |
15:05-15:35
(9-2） |
Invited: Nanoelectrochemical Switch for Reconfigurable
Logic [LEAP] T. Sakamoto |
15:35-15:55
(9-3） |
Electric-field Control of Mott Transition
in (Nd,Sm)NiO3 Electric Double Layer Transistor [1AIST, 2JST-CREST, 3Univ. of Tokyo, 4JST-PRESTO, 5RIKEN] S. Asanuma1, 2, P.-H. Xiang1, 2, H. Yamada1, H. Sato1, 2, I. H. Inoue1, 2, H. Akoh1, 2, A. Sawa1, 2, K. Ueno3, 4, M. Kawasaki3, 5, and Y. Iwasa3, 5 |
15:55-16:15
(9-4） |
Wafer-level Chip Scale Package for White
LED with High Thermal Dissipation [Toshiba]
Y. Akimoto, A. Kojima, M. Shimada, H. Tomizawa,
H. Furuyama, S. Obata, K. Higuchi, Y. Sugizaki,
and H. Shibata |
| 16:15-16:30 |
(Break 15 min) |
16:30-17:00
(9-5） |
Invited: 3-D Phase Change Memory with Poly-Si Selection
Device [Hitachi] Y. Sasago, M. Kinoshita,
H. Minemura, Y. Anzai, Y. Fujisaki, and T.
Kobayashi |
17:00-17:20
(9-6） |
Superlattice Phase Change Memory Fabrication
Process for BEOL Devices
[1LEAP, 2AIST] T. Ohyanagi1, N. Takaura1, M. Kitamura1, M. Tai1, M. Kinoshita1, K. Akita1, T. Morikawa1, and J. Tominaga2 |
17:20-17:40
(9-7） |
Composition control of GeSbTe films by Chemical
Vapor Deposition with tellurization
technique
[1Meiji Univ., 2Gas-phase Growth, 3Toyota Technological Inst.] T. Uno1, K. Suda1, N. Sawamoto1, H . Machida2, M. Ishikawa2, H. Sudo2, Y. Ohshita3, and A. Ogura1 |
| 17:40-17:50 |
Closing Remarks: J. Koike [Tohoku Univ.] |
|
