Advanced Metallization Conference 2021
30thAnniversary, Asian Session

　　

Publication of ADMETA commemorative booklet:
　　　Chapter 1:
　　　　　List of ADMETA Invited Speakers and ADMETA AWARD Winners

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　 List of ADMETA Invited Speakers

(1989)
"Surface reactions in the chemical vapor deposition of tungsten on Al, PtSi, and TiN using WF6/SiH4 mixtures", M. L. Yu, et al. (IBM)

"Mechanism for selective chemical vapor deposition of tungsten film on Si and Al surface employing WF6 and SiH4", H. ltoh et al., (Toshiba)

"Selective deposition of tungsten on oxide utilizing silicon and tungsten inplants", D. C. Thomas et al, (Cornell Univ)

"Metal CVD Technologies for ULSI interconnection", Y. Arita (NTT LSI Lab.)

"Comparison of calculated and experimental step coverage of the SiH4/WF6 and H2/WF6 chemistries using in the blanket deposition of tungsten", J. E. Schmitz et al. (Phillips Research Laboratories)

(1991)
"Recent advances in multilevel interconnections for ULSI" R. V. Joshi et al. (IBM)

"Deposition mechanism of copper CVD", N. Awaya and Y. Arita (NTT)

"Copper metallization for ULSI", M. E. Gross and V. M. Donnely (AT&T Bell Laboratories)

(1993)
"Recent developments in quarter micron interconnect technologies for 256 Mbit DRAMs", T. Kikkawa (NEC)

"Issues in multilevel interconnection technology viewed from device standpoint", K. Suguro and H. Shibata (Toshiba)

"Adhesion and encapsulation of copper films by refractory metal additions", T. L. Alford et al. (Arizona State Univ.)

"Low temperature deposition of TiN in an ECR plasma enhanced process", A. Weber et al. (Fraunhofer Institute)

"Barrier layers for ULSI metallization", G. Sandhu (Micron semiconductor) "Realization of very low resistivities and interface studies of metal/silicon contact", Y. Yasuda and S. Zaima (Nagoya Univ.)

"Thermal Stability of Epitaxial Al-Si interface", N. Thangaraj, et al. (NCEM, Lawrence Berkeley Lab.)

"Stress in chemical vapor deposited tungsten films for IC applications", G. J. Leusink et al. (Delft University of Technology)

(1995)
Keynote "Development of ULSI interconnect scheme", Shi-Qing Qang (Sematech)

"Copper reactive ion etching using infrared light irradiation", N.Hosoi and Y.Oshita (NEC)

"Processing and chemical mechanical polishing of dual damascene Al interconnect structures", A.R.Serhuraman, et al. (Rodel. Inc.)

"F-doped Si02 for low dielectric constant films in sub-half micron ULSI multilevel interconnection", N. Hayasaka, et al. (Toshiba)

"Fluorinated oxide films", D. Carl (Novellus)

"A low temperature Al plug fill process for advanced sub-half micron ULSI interconnections", T. Konechi et al. (Texas Instruments)

"Amorphous ternary diffusion barriers for Al and Cu metallizations", J. S. Reid (Intel)

(1996)
Keynote: "Current status of 300mm wafer technology", H. Komiya (SELETE)

Keynotes : "Metallization technology in Samsung", H. D. Lee (Samsung)

(1997)
Keynote "System module with chip on chip technology for realizing true system LSIs" A. Matsuzawa (Matsushita Electric).

"Low temperature formation of C54-TiSi2 using titanium alloys", B. Cabral et al. (IBM)

"Integration Issues for soft metal CMP in inlaid metallization" J. Farkas et al. (Motorola).

"Cleaning in Cu metallization technology", V. M. Dubin, et al. (AMD).

"Low temperature chemical vapour deposition of titanium and tantalum" A. Ludviksson et al. (Univ. of New Mexico)

(1998)
Keynote: "ULSI scaling and interconnect technology", T. Kikkawa (Hiroshima university)

"Low resistivity W/WSiN/poly-Si polymetal gate electrode for 1 G DRAM and beyond", Y. Akasaka et al. (Toshiba)

"Structure integrity and reliability of Low-k interconnects", P. S. Ho, et al. (Univ. of Texas).

"Cu wiring in organic low-k interlayer dielectrics using a novel damascene process", M. lkeda et al. (Fujitsu)

"Advanced thermally stable contact technology for embedded abd gigabit metal based DRAMs", Y. Nakamura et al. (Hitachi)

"Effects of barrier/seed layer on copper microstructure", sza S. S. Wong, et al. (Stanford univ)

"Characterization of microstructure, texture, and recrystallization kinetics of electroplated copper in damascene trenches", M. E. Gross et al. (Lucent Technology)

(1999)
Keynote: "Low cost high performance DRAM interconnect technology", G. S. Sandyu (MicronTechnoIogy)

"History and future trends in DRAM technology ", M. Taguchi (Fujitsu)

"DRAM technologies for gigabit generation", S. I. Lee (Samsung)

"Current status and future trends in Low-k technology", Bin Zhao (Conexand systems/ Rockwell)

"Electromigration reliability study of submicron Cu interconnects", C. K. Hu et al. (IBM)

"Barrier metal technology for Cu", S. C. Sun (Wafertech)

"Reliability improvement of aluminum dual-damascene interconnects by low-k organic SOG inter layer dielectrics ", H. Kaneko et. Al. (Toshiba)

(2000)
Keynote: "Strategy of future ULSI metallization", L. J. Chen (National Tsing Hua Univ., Taiwan)

Keynote: "Cooperative R &D on semiconductor technology in Japan", H. Komiya (SELETE)

"Damascene metal gate technology", K. Nakajima et al. (Toshiba)

"A new method to study electromigration in Al and Cu based on the piezo-resistance effect", A. H. Verbruggem et al. (Delft University of Technology)

"Atomic layer deposition (ALD) for semiconductor needs beyond 2000" Tom seidel (Genus)

"Interconnection from design perspective", T. Sakurai (Univ. of Tokyo)

"Chip level performance improvement using triple damascene concept for the future CMOS devices", N. Oda (NEC Electron Devices)

"Dual inlaid copper and fluorine-doped TEOS BEOL integration for a high performance 0.18 um technology", M. Angyal et al. (Motorola)

(2001)
Keynote: "Issues and perspectives for high-k and low-k dielectrics", M. Hirose (AIST)

"Electro chemical mechanical deposition (ECMD)", H. Talieh (Nutool)

"Application of ALD ofA1203 to semiconductor", Ki Hyun Hwang, et al. (Samsung Electronics)

"Atomic layer CVD technology for Cu metallization", Suvi Haukka et al. (ASM).

"Bumpless interconnect using surface activated bonding method", T. Suga (Univ. of Tokyo)

(2002)
Keynote "Wiring hierarchy: Technology and system design" K. Maex (IMEC)

Keynote "Agile-Fab and maskless EB wiring" K. Okumura (Univ. of Tokyo)

"Cu dual damascene integration challenges for 0.13 um logic using FSG and Low-k intermetal dielectrics", A. Zhang et al. (Chartered semiconductor)

"Materials properties and integration of porous dielectrics", J. Waterloos et al. (Dow Chemical)

"Electromigration characteristics in multilevel Cu interconnects", H. Kawasaki (Motorola)

"Supercritical fluid technology for copper interconnect fabrication ", J. J. Watkins (Univ. of Massachusetts)

"Molded interconnect devices", M. Koyanagi (Tohoku Univ. )

"Process challenges for integrated Cu with SiLK dielectrics", J. Ganbimo et al. (IBM)

(2003)
Keynote "Multi-university research centers in USA for interconnect and device research", K. Saraswatt (Stanford Univ)

Keynote "Development of porous low-k interlayer dielectric films for 45 nm technology", T. Kikkawa (Hiroshima univ.)

"Systematic study on porosity effects of MSQ film on Cu/Low-k integration", N. Ohashi et al. (SELETE)

"Electron beam cure process for porous Low-k materials", K. Mitsuoka et al.(Toshiba)

"Defects engineering in Cu integration", D. Steve Hah (Samsung)

Electromigration reliability of damascene interconnects", S. Yokogawa (NEC Electronics)

"Barrier and seed layers for copper interconnect by atomic layer deposition", I. J. Raaijmakers (ASMI N.V.)

"Advanced Cu/Low-k interconnect technology for 65 nm and beyond", Chih-Chien Liu et al. (United Microelecffonic Corp)

"Advanced Cu/Low-k interconnects for 90/65 nm logic technologies", M. S. Liang (TSMC)

(2004)
Keynote "65 nm node Low-k/Cu interconnect-porous low-k for manufacturing", N. Kobahashi (SELETE)

Keynote "Research on CMOS interconnect technologies in the Grenoble area", M. Brillouet, (CEA/LETI)

"Stress-induced voiding in Cu interconnects" E. T. Ogawa et al. (Texas Instruments)

"Metallization technologies for DRAM" G. H. Choi, et al. (Samsung Electronics)

"Process , Integration, and reliability of TMCTD based low-k dielectric film", W. Lu et al. (Chartered Semiconductor)

"Metallization and dielectric reliability in Cu interconnects: Effect of Cap Layers and surface treatment", A. Krishnamoorthy et al. (IME, Singapore)

"Approaching and going beyond to coming Red Brick Walls in Cu and Low-k interconnects", K. A. Monnig (International SEMATECH)

"A roadmap for vertical device integration", H. B. Pogge (IBM Microelectronics)

(2005)
Keynote "A new smart stack technology for three dimensional LSI", M. Koyanagi (Tohoku Univ.)

Keynote "Advanced BEOL R&D activity at Crolles Alliance", J. Torres (ST Microelectronics)

"Interconnect technology featuring ULK stacked hybrid structures", T. Hasegawa et al. (Sony)

"Advanced electronic materials for ULSI metallization", M. E. Mills et al. (Dow Chemical)

"Electroless deposition of Co-based alloys for selective capping applications", L. M. Michaelsom (Freescale Semiconductor)

"Single wafer cleaning process on next generation device", C. Hong (Samsung Electronics)

"BEOL process integration with Cu/SiCOH (k=2.8) low-k interconnects at 65 nm ground rule", S. L. Lane (IBM)

"Self-forming barrier process with Mn addition in Cu metallization", J. Koike et al. (Tohoku Univ., STARC)

(2006)
Keynote : H. Watanabe, (Tsukuba semiconductor consortium)

Keynote: B. M. Credie (IBM)

"Low-k interconnect using self-assembled porous silica film", S. Chikaki (MIRAI)

"Issues & potential solutions for future of interconnect technology", S. H. Brongersma (IMEC)

"Interaction of microstructure with electron wind force", S. Mhaisalkar (Nanyang Technological Univ.)

"Interface characterization and properties for future generation interconnect technologies", R. H. Dauskardt (Stanford university)

"Carbon nanotube interconnect technologies", Y. Awano (Fujitsu, MIRAI-SELETE)

"Low damage process of extreme low-k dielectrics integration for 45 nm generation and beyond", C-H. Hsiech, et al. (TSMC)

*) For 2007 and later, please refer to the ADMETA HP archive.


　 ADMETA AWARD

　Since its inception, ADMETA has gradually increased the number of contribution papers, and since 2000, it has consistently accepted over 40 submissions. Therefore, the ADMATA Committee has decided to bestow an ADMETA AWARD to stimulate researchers’ participation to make presentations and further develop ADMETA. We have examined the content of the papers and lectures (presentation and Q&A) from the contribution papers since 2003, selected the best papers, and awarded the “ADMETA AWARD.” In addition to this, we have established several “Technical Achievement Award”s since 2004. The criterion for selection is that it is particularly excellent in “usefulness, originality, and presentation”. Below is a list of award-winning papers.

ADMETA Award

2003 Kazuhiko Endo , Noboru Morita, Tatsuya Usami, Koichi Ohta, and Hidenobu Miyamoto "A Highly Reliable Barrie Dielectric for Cu/SiOC Interconnects fromTrimethylvinylsilan" [Advanced Technology Development Div., NEC Electronics Corp., *Silicon System Research Lab., NEC Corp.]

2004 Fumito Shoji, T.Ohdaira, I. Suzuki, M. Shimada, R. Suzuki, and S. Ogawa "Behaviors of Vacanies in Electro-Plated Cu Films by Positron-Annihilation Lifetime Spectroscopy correlated with SIV Phenomena" [SELETE, Photonics Research Institute, AIST]

2005 Fuminori Ito, Tsuneo Takeuchi, and Yoshihiro Hayashi "Important of Mechanical Properties of Porous SiOCH film by Post-cure Treatments" [System Devices Research Laboratories, NEC Corporation]

2006 Fuminori Ito, Tsuneo Takeuchi, and Yoshihiro Hayashi "Photo-stimulated Desorption from Porous Low-k Films by UV Cure Treatments with Various Wavelength" [System Devices Research Laboratories, NEC Corp.]

2007 K. Kawamura, S. Akiyama, K. Ohkubo, N. Idani, T. Shirasu, S. Takesako, A. Asneil, M. Sato, T. Oshima, H. Sakai, K. Yanai, M. Nakaishi, N. Shimizu, H. Watatani, and M. Kase " Barrier metal integration for copper conatacts on nickel silicide " [Fujitsu Lab., Fujitsu]

2008 T. Kirimura, Y. Iba, S. Ozaki, Y. Kobayashi and Y. Nakata " Effect of Surface Roughness on Plasma-induced Degradation of Porous Low-k Material " [Fujitsu Lab., Fujitsu]

2009 M. Wada, T. Kurusu, Y. Akimoto, N. Matsunaga, H. Tanimoto, N. Aoki, Y. Toyoshima, and H. Shibata " A Study on Resistivity Increase of Copper Interconnects with the Dimension Comparable to Electron Mean Free Path Utilizing Monte Carlo Simulation " [Toshiba]

2010 S. Yokogawa, and Y. Kakuhara " Role of Impurity Segregation to Cu/Cap Interface and Grain Boundary on Resistivity and Electromigration in Cu/Low-k Interconnects " [Renesas Electronics]

2011 H. Kitada, Y. Morikawa, N. Maeda, K. Fujimoto, S. Kodama, Y.S. Kim, Y. Mizushima, T. Nakamura, and T. Ohba " Surface Microroughness-induced Leakage Current in Through-Silicon Via Interconnects " [Univ.of Tokyo, Fujitsu Lab.]

2012 H. Miki, A. Isobayashi, A. Kajita, Y. Sugizaki, and H. Shibata " Airgap Formation in Ultra Fine Wire Spacing and Its Wire-to-Wire Leakage Characteristics " [Toshiba]

2013 Y. Mizushima, Y. Kim, T. Nakamura, R. Sugie, H. Hashimoto, A. Uedono, and T. Ohba " Impact of Back Grind Damage on Si Wafer Thinning for 3D Integration " [Fujitsu Laboratories, Tokyo Institute of Technology, Disco Toray Research Center, Univ. of Tsukuba]

2014 A. Isobayashi, M. Wada, B. Ito, T. Saito, D. Nishide, T. Ishikura, M. Katagiri, Y. Yamazaki, T. Matsumoto, M. Kitamura, M. Watanabe, N. Sakuma, A. Kajita, and T. Sakai " CNT Via Integration with Highly Dense and Selective CNT Growth " [LEAP]

2015 B.-J. Kim, S. Jung, D.-G. Kim, O. Kraft, I.-S. Choi, and Y.-C. Joo " Mechanical Reliability of Metal Interconnecton Polymer Substrate " [K Institute of Matelials Science, Karlsruhe Institute of Technology, Korea Institute of Science and Technology, Seoul National University]

2016 E. Kondoh, T. Kawakami, M. Watanabe, L. Jin, S. Hamada, S. Shima, and H. Hiyama " In-situ ellipsometry of Cu surfaces immersed in BTA-H2O2 solutions-Effect of pH " [Univ. of Yamanashi, Ebara]

2017 R. Ifuku, T. Matsumoto, T. Sakai, and A. Kajita " Catalyst-free Growth of Graphene on 300mm Dielectric Substrate by Microwave Plasma Enhanced Chemical Vapor Deposition at Low Temperatures " [Tokyo Electron, Toshiba]

2018 W. Feng, N. Watanabe, H. Shimamoto, M. Aoyagi, and K. Kikuchi " Thermal Stress Investigation of Annular-Trench-Isolated Through Silicon Via (TSV) " [AIST]

2019 H. Hashiguchi, M. Haneda, Y. Kagawa, M. Horiike, T. Hirano, S. Kobayashi, T. Hirano, and H. Iwamoto " Study of Cu pad thermal expansion effect on fine-pitch Cu-Cu hybrid bonding technology " [Sony Semiconductor Solutions Corporation]

Technical Achievement Award

2004 F. Ito, K. Hijioka, T. Takeuchi, and Y. Hayashi " Nanostructure Control of Porous Low-k Dielectlic Films with High Water Resistance " [NEC]

2004 I. Noji, I. Kobata, H. Yasuda, T.Iizumi, M. Kumekawa, Y. Wada, A. Fukunaga, M. Tsujimura, Y. Toma, T. Suzuki, and T. Saitoh " Application of Electro-Chemical Polishing in DI Water to Cu Damascene Wiring Planarization Process" [Ebara, EbaraResearch]

2004 Y. Iba, N. Misawa, I. Sugiura, N. Nishikawa, F. Sugimoto, Y. Setta, H. Kitada, Y. Koura, Y. Nakata, J. Nakahira, K. Nakano, A. Hasegawa, M. Nakanishi, N. Shimizu, S. Fukuyama, E. Yano, and M. Miyajima "Dual Damascene Formation Technique using Nano -Clustering Silica(NCS) for 65nm Node Interconnects" [Fujitsu Ltd., Fujitsu Lab.]

2005 M. Kodera, S. Kakinuma, Y. Saijo, M. Tsujimuia and G. Pezzotti " Nanometer -Scale Stress Detection of Patterned ILD Using Cathodolmninescence Piezo-Spectroscopic Assessments in a Nano-Stress Microscope " [Toshiba, *Horiba, Ebara, Kyoto Institute of Technology]

2005 C. Guedj, V. Arnal, M. Aimadeddine, J.F. Guillaumond, L.Arnaud, J. P.Barnes, L. L. Chapelon, G. Reimbold, J. Torres, G, Passemard and F. Boulanger " Thermal Dependence of Leakage Pathways in Cu / ULK Advanced Interconnects " [CEA-DRT -LETI/DTS -CEA/GRE, ST Microelectronics]

2006 H. Sakai, N. Shimizu, N. Ohtsuka, T. Tabira, T. Kouno, M. Nakaishi and M. Miyajima " Novel PVD Process of Barrier Metal for Cu Interconnects Extendable to 45nm Node and Beyond " [Fujitsu, Fujitsu Lab]

2006 K. Okada, H. Ito and K. Masu " On-Chip Differential-Line(DTL) Interconnect for 22nm Technology " [Tokyo Institute of Technology]

2007 M, Sunayama, H. Iwata, M. Terahara, M. Nakaishi and N. Shimizu " Impurities in Electroplated Copper Interconnects " [Fujitsu Lab., Fujitsu]

2007 F. Ito, T. Takeuchi, H. Yamamoto, T. Ohdaira, R. Suzuki, and Y. Hayashi " Pore-Connectivity Dependence of Moisture Absorption into Porous Low-k Films by Positron-Annihilation Lifetime Spectroscopy " [NEC, AIST]

2007 K. Kinoshita, S. Chikaki, E. Soda, K. Tomioka, H. Tanaka, K. Kohmura, T. Nakayama, T. Kikkawa and S. Saito " Process Induced Damages and Recovery by Silylation for Low- k/Cu Interconnects with Highly- Porous Self-Assembled Silica Film " [Selete, Mitsui Chemicals, ULVAC, AIST]

2008 E. Kondoh, S. Aruga, F. Ito and Y. Hayashi " A Fast New Approach for Evaluating the Connectivity of Micropores (<2 nm) and Supermicropores (<0.5 nm) in Low-k ThinFilms " [Univ. of Yamanashi, NEC Electronics]

2008 N. Maeda, H. Kitada,K. Fujimoto, K. Suzuki, T. Nakamura and T. Ohba " Novel and Production-Worthy Wafer-on-a-Wafer (WOW) Technology Using Self-Aligned TSV (SALT) Interconnects " [Univ. of Tokyo, *Dai Nippon Printing, Fujitsu Lab.]

2008 T. Harada, A. Ueki, S. Kido, K. Tomita, Y. Kanda, T. Sasaki, H. Tsuji, T. Furuhashi,T. Kabe, J. Shibata, A. Iwasaki, J. Izumitani, S. Matsumoto, Y. Kawano, and T. Ueda " Air Gap Integration of 45nm Node Cu Interconnects and Evaluations of Electrical and Mechanical Characteristics " [Matsushita Electric Industrial, Renesas Technology, Panasonic Semi-Conductor Engineering]

2009 Y. Fujii, Y. Sutou, K. Neishi, and J. Koike " Selective Formation of a SnO2 Cap Layer, Its Growth Behavior, and Oxidation Resistance " [Tohiku Univ.]

2009 N. Shimizu, N. Tajima, T. Kada, S. Nagano, Y. Ohashi and S. Hasaka " Novel Precursor for Development of Si-C2H4-SI Networks in SiCH for Application as a Low-k Cap Layer beyond the 22 nm Node " [Taiyo-Nippon Sanso,NIMS,Tri Chemical Lab.]

2010 M. katagiri,Y. Yamazaki, M. Wada, M. Kitamura, N. Sakuma, M. Suzuki, S. Sato, M. Nihei, A. Kajita, T. Sakai and Y. Awano " Improvement in Electrical Properties of Carbon Nanotube Via.Interconnects " [MIRAI-Selete,Toshiba]

2010 H.-B. Lee, T. Matsuda, J.-H. Kang, H.-K. Jung, J.-W. Hong, J.-H. Yun, J.-S. Park, J.-M. Lee, L-S. Park, G.-H. Choi, S. Choi, and C. Chung " CVD Cobalt as an Enhancement Layer to Improve Cu/Low-k Interconnect Performance " [Samsung Electronics]

2010 H. Kitada, N. Maeda’, K. Fujimoto,Y. Mizushima, Y. Nakata, T. Nakamura, and T. Ohba " Stress and Diffusion Resistance of Low Temperature CVD Dielectrics for Multi-TSVs on Bumpless Wafer-on-Wafer (WOW) Technology " [The University of Tokyo, Fujitsu Laboratories., Dai Nippon Printing]

2010 C. Kobayashi, Y. Miura, S. Nagano, K. Ohto, H. Shimizu, T. kada, T. Ohira, T. Usami, and K. Fujii " Highly Hermetic Barrier Low-k SiC (k<3.5) by Using New Precursor for 28 nm-Node Devices and beyond" [Renesas Electronics, Taiyo-Nippon Sanso , Tri Chemical Laboratories]

2011 S. Yokogawa, H. Tsuchiya, and T. Shimizu " Modified Thermal Response Model for Joule Heating of Multi-level Cu/Low-k Interconnects " [Renesas Electronics]

2012 A. Kurokawa,Y. Sutou, J. Koike, T. Hamada, K. Matsumoto, H. Nagai, K.Maekawa, H. Kanato'’ "Simultaneous Formation of a Metallic Mn Layer and a MnOx /MnSixOy Barrier Layer by Chemical Vapor Deposition at 250°C" [Tohoku Univ., Tokyo Electron, TEL Technology Center, Ube Industries]

2012 Y. Akimoto, A. Kojima, M. Shimada, H. Tomizawa, H. Furuyama, S. Obata, K. Higuchi, Y.Sugizaki, and H. Shibata "Wafer-level Chip Scale Package for White LED with High Thermal Dissipation" [Toshiba]

2013 M. Watanabe,Y. Takeuchi, T. Ueno, M. Matsubara, E. Kondoh, S.Yamamoto, N. Kikukawa, and T. Suemasu " Cu Coating Inside Ultra High-aspect-ratio(>130) and Bended Through-hole Using Supercritical CO2 Fluid " [Univ. of Yamanashi, Fujikura]

2014 O. Nakatsuka, Y. Deng, M. Sakashita, and S. Zaima " Formation of Epitaxial NiGe Layer on Ge (001) Substrate and Influence of Interfece Structure on Schottky Barrier Height" [Nagoya Univ.]

2014 A. Gawase, H. Eda, T. Kawasaki, K. Iwade, and Y. Matsui " Investigation of Micro-Scratches Generation Focused on the Scratches Shapes in Chemical Mechanical Polishing Process" [Toshiba]

2015 M. Katagiri, T. Matsumoto, H. Miyazaki, R. Ifuku, R. Matsumoto, T. Sakai, and A. Kajita "Resistivity Reduction of Multilayer Graphene Interconnects Prepared by Low-Temperature Chemical Vapor Deposition" [Toshiba, Tokyo Electron, Tokyo Polytechnic University]

2016 M. Hosseini, Y. Sutou, and J. Koike "Thermal stability and diffusion barrier property of a Co-Ti layer for advanced copper metallization" [Tohoku Univ.]

2016 P. Ventzek, J. Yoshikawa, M. Matsukuma, T. Kato T. Nakano, H. Ueda, A. Ranjan, T. Iwao, K. Ishibashi, G. S. Hwang, and G. Hartmann " Atomistic methods in dielectric materials deposition and removal processes " [Tokyo Electron America, Tokyo Electron Miyagi, Tokyo Electron, Tokyo Electron Technology Center America, Tokyo Electron Tohoku, Univ. of Texas at Austin] 2017 K. Miyano, M. Tsukui, H. Nago, Y. lyechika, T. Kobayashi, Y. Ishikawa, H. Takahashi, S. Mitani, and T. Yoda " The Origin and Suppression of Critical Deep-Pit in the HEMT Structure Using GaN on Si Teclnology with Strained Layer Super Lattice" [NuFlare Technology]

2019 J. Suh, Q. Li, J. van de Groep, M. Brongersma and K. C. Saraswat " Vertically Stacked Suspended SiGe/Ge Nanowires Fabricated by 3D Ge Condensation for Optoelectronic Applications " [Stanford University]

ADMETA Poster Award

2010 C. Kobayashi, Y.Miura, S.Nagano, K. Ohto, H.Shimizu, T. kada, T.Ohira, T. Usami, and K. Fujii "Highly Hametic Barrier Low-k SiC (k<3.5) by Using New Precursor for 28 nm-Node Devices and beyond [Renesas Electronics, Taiyo-Nippon Sanso, Tii ChemicalLaboratorie" [Univ. of Tokyo]

2011 T. Momose, M. Sugiyama, and Y. Shimogaki "Mass Production Reactor design for Cu Interconnects on 12-inch Wafers Using Supercritical Fluid Deposition" [Univ. of Tokyo]

2012 B.T. Bae, and J. Koike "Electrical Contact Property and Interface Microstructure of Cu-Si Alloy on n-GaAs" [Tohoku Univ.]

2013 Y. Tsuchiya, Y. Sutou, J. Koike, H. Kanato, and K. Watanuki " Formation of Mn Barrier Layer on Porous SiOC by Chemical Vapor Deposition " [Tohoku Univ., Ube Industries]

2014 E. Kondoh, Y. Tamegai, M. Watanabe, and L. Jin " Selective Cu fill into nanopores using supercritical carbon dioxide" [Univ. of Yamanashi]

2015 M. Son, S. Chung, K. Kim, and M.-H. Ham " Cu/graphene heterostructures for advanced interconnects: direct growth of graphene on Cu interconnects" [Gwangju Institute of Science and Technology]

2016 N. Okamoto, K. Kataoka, and T. Saito "Sulfide Semiconductor Materials prepared by High-speed Electrodeposition and Discussion of Electrochemical Reaction Mechanism" [Osaka Prefecture Univ.]

2017 Y. Mizushima, Y. Kim, S. Kodama, T. Nakamura, and T. Ohba "Plan view stress distribution at 1m underneath of DRAM device using WOW ultra-thinning technology" [Fujitsu Lab., Tokyo Institute of Technology]

2018 Y.-T. Hsu, I.-H. Tseng, C. Chen, and J. Leu " Thermal stress relaxation in electroplated nano-twinned copper film " [National Chiao Tung University]

2019 M. B. Takeyama1, M. Sato, and M. Yasuda " Cu(111) orientation control on thin TaWN alloy barrier " [Kitami Institute of Technology, Toray Research Center, Inc.]

2019 S.-W. Fan, Y.-L. Hsu, and J. Leu " Plasma-enhanced Atomic Layer Deposition of Low-k Silicon Carbonitride Films " [National Chiao Tung University]



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